In the manufacture of semiconductor integrated circuits utilizing field effect transistors, it is often necessary to form electrical contacts to either the source or drain region. Various techniques and structures have been devised for forming contacts to source or drain regions.
In the design of Static Random Access Memories (SRAMs) it is generally necessary to connect the source/drain of an access transistor to the gate of a pull-down transistor. For example, in FIG. 1, the junctions denoted by reference numerals 11 and 13 provide instances in which, for example, the gate of pull-down transistor 15 is connected to the source/drain of access transistor 19 or, the gate of pull-down transistor 17 is connected to the source/drain of access transistor 21.
In conventional SRAM fabrication, one of the connections (11 or 15) is made at the so-called "poly-1" level. That is, the polysilicon which forms the gate of the respective pull-down transistor is patterned over the source/drain region of the access transistor, thereby forming a direct contact. The other access/pull-down connection is often made at a higher level of the integrated circuit (i.e., perhaps at the "poly-2" level or higher).
FIGS. 2-5 illustrate a problem which occurs when a polysilicon gate is patterned directly over a source/drain. In FIG. 2, reference numeral 23 denotes a substrate which may be, typically, silicon, epitaxial silicon, doped silicon, etc. In general, the term substrate refers to a material or to a layer upon which other materials may be subsequently formed. Reference numeral 25 denotes a junction region which comprises the source or drain of an access transistor, such as transistors 19 or 21 in FIG. 1. Reference numeral 27 denotes a dielectric layer which, typically, may be silicon dioxide or silicon oxynitride. If layer 27 is silicon dioxide, it may typically have a thickness of approximately 100 .ANG.. In FIG. 3, layer 27 has been patterned exposing surface 29 of junction 25. In FIG. 4, polysilicon layer 31 has been deposited to cover exposed surface 29 of junction 25. It is desired that polysilicon layer 31 should be patterned using a photoresist. Photoresist 33 is subsequently deposited over polysilicon layer 31 and patterned. It is desirable that edge 35 of photoresist 33 be immediately above (or, in FIG. 4, to the left of) edge 37 of patterned dielectric 27.
Should edge 35 of photoresist 33 be slightly misaligned (and, as shown in FIG. 4, somewhat to the right of edge 37 of dielectric 27, i.e., should edge 35 overlie the opening defined by edge 37 of dielectric 27), subsequent exposure of polysilicon layer 31 to an etchant species may cause trenching into junction 25 of substrate 23. The trenching may damage the electrical characteristics of the junction and, under worst circumstances, may completely penetrate junction 25. Thus, an examination of FIGS. 4 and 5 shows that, if patterned edge 35 of resist 33 is positioned parallel with, or to the left of, patterned edge 37 of dielectric 27 (i.e., edge 35 overlies layer 27), subsequent etching will stop on dielectric 27 and not damage junction 25. However, should patterned edge 35 or photoresist 33 be to the right of patterned edge 37 of dielectric 27, the trench 39 depicted in FIG. 5 may be obtained.